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NCP5386, NCP5386A, NCP5386B 1/2 Phase Controller for CPU and Chipset Applications
The NCP5386 is a one- or two-phase buck controller which combines differential voltage and current sensing, and adaptive voltage positioning to power both AMD and Intel processors and chipsets. Dual-edge pulse-width modulation (PWM) combined with inductor current sensing reduces system cost by providing the fastest initial response to transient load events. Dual-edge multi-phase modulation reduces total bulk and ceramic output capacitance required to satisfy transient load-line regulation. A high performance operational error amplifier is provided, which allows easy compensation of the system. The proprietary method of Dynamic Reference Injection (Patented) makes the error amplifier compensation virtually independent of the system response to VID changes, eliminating tradeoffs between overshoot and dynamic VID performance.
Features http://onsemi.com MARKING DIAGRAMS
1
1
32
NCP5386x AWLYYWWG
QFN32, 5 x 5* MN SUFFIX CASE 485AF *Pin 33 is the thermal pad on the bottom of the device. NCP5386 = Specific Device Code x = Blank, A or B A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package
* Meets Intel's VR 10.0 and 11.0, and AMD Specifications * No load Intel VR Offset of -19 mV (NCP5386), +20 mV * * * * * * * * * * * * * * * * *
(NCP5386A), and 0 mV (NCP5386B) Dual-Edge PWM for Fastest Initial Response to Transient Loading High Performance Operational Error Amplifier Supports both VR11 and Legacy Soft-Start Modes Dynamic Reference Injection (Patent# 7057381) DAC Range from 0.5 V to 1.6 V "0.5% System Voltage Accuracy from 1.0 V to 1.6 V True Differential Remote Voltage Sensing Amplifier Phase-to-Phase Current Balancing "Lossless" Differential Inductor Current Sensing Differential Current Sense Amplifiers for each Phase Adaptive Voltage Positioning (AVP) Frequency Range: 100 kHz - 1.0 MHz OVP with Resettable, 8 Event Delayed Latch Threshold Sensitive Enable Pin for VTT Sensing Power Good Output with Internal Delays Programmable Soft-Start Time This is a Pb-Free Device*
ORDERING INFORMATION
Device NCP5386MNR2G* NCP5386AMNR2G* NCP5386BMNR2G* Package QFN32 (Pb-Free) QFN32 (Pb-Free) QFN32 (Pb-Free) Shipping 2500 / Tape & Reel 2500 / Tape & Reel 2500 / Tape & Reel
*Temperature Range: 0C to 85C For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
Applications
* Desktop Processors and Chipsets * Server Processors and Chipsets * DDR
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2008
May, 2008 - Rev. 1
1
Publication Order Number: NCP5386/D
NCP5386, NCP5386A, NCP5386B
32 31 30 29 28 27 26 12VMON 25 G2
NTC
VR_FAN
VID0
1 2 3 4 5 6 7 8
VR_RDY
VCC
EN
VID1 VID2 VID3 VID4 VID5 VID6 VID7 DACMODE
G1 DRVON CS2
24 23 22 21 20 19 18 17
NCP5386/A/B 1/2-Phase Buck Controller (QFN32) AGND Down-Bonded to Exposed Flag
DIFFOUT COMP ROSC ILIM VS- VS+ NC
CS2N CS1 CS1N VDRP VFB
9
SS
10
11
12
13
14
15
Figure 1. Pin Connections
(Top View)
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2
16
NCP5386, NCP5386A, NCP5386B
+5 V VTT 680 W PULLUPS RVCC +5 V CVCC1 RNTC1 U1 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VR_EN VR_RDY VR_FAN VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 DACMODE EN VR_RDY VR_FAN VS- VS+ RISO1 RISO2 CS2 CS2N NCP3418 VCC OD RT2 BST DRVH SW DRVL IN CFB1 RFB VFB RDRP VDRP CD1 RD1 COMP ILIM ROSC SS DRVON RFB1 DIFFOUT CS2 PGND RS2 G1 CS1 CS1N G2 GND 12VMON NTC RT1 RNTC2 NCP3418B VCC OD IN BST DRVH SW DRVL PGND RS1 C4 12 V_FILTER 12 V_FILTER
CS1
12 V_FILTER
12 V_FILTER
NCP5386/A/B
CF
RF
CH RVFB RLIM1 CSS
RLIM2
RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP + VSSP CPU/MCH GND
Figure 2. 2-Phase Application Schematic
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NCP5386, NCP5386A, NCP5386B
+5 V VTT 680 W PULLUPS RVCC +5 V CVCC1 RNTC1 U1 VCC VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID_SEL VR_EN VR_RDY VR_FAN VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 DACMODE EN VR_RDY VR_FAN VS- VS+ RISO1 RISO2 CS2 CS2N G1 CS1 CS1N DGND 12VMON NTC RNTC2 NCP3418B VCC OD IN RT1 BST DRVH SW DRVL PGND RS1 12 V_FILTER 12 V_FILTER
CS1
RT2
NCP5386/A/B
CFB1 RFB
RFB1 DIFFOUT VFB RDRP VDRP DRVON
CD1
RD1 COMP
CF
RF
ILIM
ROSC SS
CH RVFB RLIM1
CSS
RLIM2
RT2 LOCATED NEAR OUTPUT INDUCTORS VCCP + VSSP CPU/MCH GND
Figure 3. 1-Phase Application Schematic
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NCP5386, NCP5386A, NCP5386B
DACMODE VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 SS
NCP5386/A/B VR10/11/AMD DAC + DAC
NTC VR_FAN NTC
VS- VS+ DIFFOUT
+ Diff Amp Fault 1.3 V + Error Amp Droop Amplifier 1.3 V
+-
VFB COMP VDRP
GND
CS1 CS1N CS2 CS2N
+ Gain = 6
+ -
ENB
G1
+ Gain = 6
+ -
ENB
G2
OVER
Oscillator ROSC DIFFOUT
Fault
+ ILIM EN VCC ILimit
+ VCC UVLO + 12VMON UVLO
Fault Logic 3 Phase Detect and Monitor Circuits
DRVON
VR_RDY
12VMON
Figure 4. Simplified Block Diagram http://onsemi.com
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NCP5386, NCP5386A, NCP5386B
PIN DESCRIPTIONS
QFN32 Pin No. 32, 1 - 7 8 9 10 Symbol VID0-VID7 DACMODE SS ROSC Voltage ID DAC inputs VRM select bit A capacitor from this pin to ground programs the soft-start time. A resistance from this pin to ground programs the oscillator frequency. Also, this pin supplies an output voltage of 2 V which may be used to form a voltage divider to the ILIM pin to set the over-current shutdown threshold as shown in the Applications Schematics. Overcurrent shutdown threshold. To program the shutdown threshold, connect this pin to the ROSC pin via a resistor divider as shown in the Applications Schematics. To disable the over-current feature, connect this pin directly to the ROSC pin. To guarantee correct operation, this pin should only be connected to the voltage generated by the ROSC pin; do not connect this pin to any externally generated voltages. Do not connect anything to this pin. Non-inverting input to the internal differential remote sense amplifier Inverting input to the internal differential remote sense amplifier Output of the differential remote sense amplifier Output of the error amplifier, and the non-inverting input of the PWM comparators Error amplifier inverting input. Connect a resistor from this pin to DIFFOUT. The value of this resistor and the amount of current from the droop resistor (RDRP) will set the amount of output voltage droop (AVP) during load. Current signal output for Adaptive Voltage Positioning (AVP). The voltage of this pin above the 1.3 V internal offset voltage is proportional to the output current. Connect a resistor from this pin to VFB to set the amount of AVP current into the feedback resistor (RFB) to produce an output voltage droop. Leave this pin open for no AVP. Inverting input to current sense amplifier. Non-inverting input to current sense amplifier. Output to enable Gate Drivers PWM output pulses to gate drivers Second UVLO monitor for monitoring the power stage supply rail Power for the internal control circuits. Voltage Regulator Ready (Power Good) output. Open drain output that indicates the output is regulating. Remote temperature sense connection. Connect an NTC thermistor from this pin to GND and a resistor from this pin to VREF. As the NTC's temperature increases, the voltage on this pin will decrease. Open drain output that will be low impedance when the voltage at the NTC pin is above the specified threshold. This pin will transition to a high impedance state when the voltage at the NTC pin decreases below the specified threshold. This pin requires an external pull-up resistor. Pull this pin high to enable controller. Pull this pin low to disable controller. Either an open-collector output (with a pull-up resistor) or a logic gate (CMOS or totem-pole output) may be used to drive this pin. A Low-to-High transition on this pin will initiate a soft start. Connect this pin directly to VREF if the Enable function is not required. 20 MHz filtering at this pin is required. Power supply return (QFN Flag) Description
11
ILIM
12 13 14 15 16 17
NC VS+ VS- DIFFOUT COMP VFB
18
VDRP
19, 21 20, 22 23 24, 25 26 27 28 29 30
CS1N, CS2N CS1, CS2 DRVON G1, G2 12VMON VCC VR_RDY NTC VR_FAN
31
EN
33
GND
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NCP5386, NCP5386A, NCP5386B
MAXIMUM RATINGS
Electrical Information Pin Symbol COMP VDRP VS+ VS- DIFFOUT VR_RDY, VR_FAN VCC ROSC DACMODE, EN All Other Pins *All signals reference to GND unless otherwise noted. Thermal Information Rating Thermal Characteristic, QFN Package (Note 1) Symbol RqJA TJ TA TSTG MSL Value 56 0 to 125 0 to 85 -55 to +150 1 Unit C/W C C C VMAX (V) 5.5 5.5 2.0 2.0 5.5 5.5 7.0 5.5 3.5 5.5 VMIN (V) -0.3 -0.3 GND - 300 mV GND - 300 mV -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 ISOURCE (mA) 10 5 1 1 20 N/A N/A 1 0 - ISINK (mA) 10 5 1 1 20 20 20 N/A 0 -
Operating Junction Temperature Range (Note 2) Operating Ambient Temperature Range Maximum Storage Temperature Range Moisture Sensitivity Level, QFN Package
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. *The maximum package power dissipation must be observed. 1. JESD 51-5 (1S2P Direct-Attach Method) with 0 Airflow. 2. JESD 51-7 (1S2P Direct-Attach Method) with 0 Airflow.
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Error Amplifier Input Bias Current Input Offset Voltage (Note 3) Open Loop DC Gain (Note 3) Open Loop Unity Gain Bandwidth (Note 3) Open Loop Phase Margin (Note 3) Slew Rate (Note 3) CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND CL = 60 pF to GND, RL = 10 kW to GND DVIN = 100 mV, G = -10 V/V, 1.5 V < COMP < 2.5 V, CL = 60 pF, DC Load = 125 mA 10 mV of Overdrive ISOURCE = 2.0 mA 10 mV of Overdrive ISINK = 2.0 mA -200 -1.0 - - - - - - 100 15 70 5 200 1.0 - - - - nA mV dB MHz V/ms Test Conditions Min Typ Max Units
Maximum Output Voltage Minimum Output Voltage
2.20 -
VCC - 20 mV 0.01
- 0.5
V V
3. Guaranteed by design. Not tested in production.
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NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Error Amplifier Output Source Current (Note 3) Output Sink Current (Note 3) Differential Summing Amplifier VS+ Input Resistance VS+ Input Bias Voltage VS- Bias Current VS+ Input Voltage Range VS- Input Voltage Range DC Gain VS+ to DIFFOUT DAC Accuracy (measured at VS+) DRVON = Low DRVON = High DRVON = Low DRVON = High VS- = 0 V 0.95 v DDIFFOUT / DVS- v 1.05 0.5 V v DIFFOUT v 2.0 V 0.95 v DDIFFOUT / DVS- v 1.05 0.5 V v DIFFOUT v 2.0 V 0 V v DAC - VS+ v 0.3 V Closed loop measurement including error amplifier. (See Figure 20) 1.0 v DAC v 1.6 0.8 v DAC v 1.0 0.5 v DAC v 0.8 CL = 80 pF to GND, RL = 10 kW to GND DVIN = 100 mV, DIFFOUT = 1.3 V to 1.2 V VS+ - DAC = 1.0 V ISOURCE = 2.0 mA VS+ - DAC = -0.8 V ISINK = 2.0 mA VS+ - DAC = 1.0 V DIFFOUT = 1.0 V VS+ - DAC = -0.8 V DIFFOUT = 1.0 V - - - - - -0.3 -0.3 0.99 1.5 17 0.05 0.65 33 - - - - - - - - 2.0 0.3 1.01 kW V mA V V V/V 10 mV Input Overdrive COMP = 2.0 V 10 mV Input Overdrive COMP = 1.0 V 2.0 2.0 - - - - mA mA Test Conditions Min Typ Max Units
-0.5 -5 -8 - - 2.0 - 2.0 2.0
- - - 10 5.0 3.0 0.01 - -
0.5 5 8 - - - 0.5 - -
% mV mV MHz V/ms V V mA mA
-3dB Bandwidth (Note 3) Slew Rate (Note 3) Maximum Output Voltage Minimum Output Voltage Output Source Current (Note 3) Output Sink Current Internal Offset Voltage VDRP pin offset voltage AND Error Amp input voltage
-
1.30
V
VDRP Adaptive Voltage-Positioning Amplifier Current Sense Input to VDRP Gain Current Sense Input to VDRP -3dB Bandwidth (Note 3) VDRP Output Slew Rate (Note 3) -60 mV < (CSx-CSxN) < +60 mV (Each CS Input Independently) CL = 30 pF to GND, RL = 10 kW to GND DVIN = 25 mV 1.3 V < VDRP < 1.9 V, CL = 330 pF to GND, RL = 1 kW to 10 kW connected to 1.3 V CSx= CSxN = 1.3 V CSx - CSxN = 0.1 V (all phases), ISOURCE = 1.0 mA 5.64 - 2.5 5.79 4 - 5.95 - - V/V MHz V/ms
VDRP Output Voltage Offset from Internal Offset Voltage Maximum VDRP Output Voltage
-15 2.6
- 3.0
+15 -
mV V
3. Guaranteed by design. Not tested in production.
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NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter VDRP Adaptive Voltage-Positioning Amplifier Minimum VDRP Output Voltage Output Source Current (Note 3) Output Sink Current (Note 3) Current Sense Amplifiers Input Bias Current Common Mode Input Voltage Range Differential Mode Input Voltage Range (Note 3) Input Referred Offset Voltage (Note 3) Current Sense Input to PWM Gain Oscillator Switching Frequency Range (Note 3) Switching Frequency Accuracy ROSC = 50 kW 25 kW 10 kW 100 196 380 803 - - 1.950 - - - - 5 10 2.010 1000 226 420 981 - - 2.065 kHz kHz CSx = CSxN = 1.0 V 0 V < (CSx - CSxN) < 0.1 V CSx = CSxN = 1.4 V -200 -0.3 -120 -1.0 - - - - - 6.0 200 2.0 120 1.0 - nA V mV mV V/V CSx - CSxN = -0.033 V (all phases), ISINK = 1.0 mA VDRP = 2.0 V VDRP = 1.0 V - - - 0.1 1.3 25 0.5 - - V mA mA Test Conditions Min Typ Max Units
Switching Frequency Tolerance (Note 3) ROSC Output Voltage Modulators (PWM Comparators) Minimum Pulse Width (Note 3) Propagation Delay (Note 3) Magnitude of the PWM Ramp 0% Duty Cycle 100% Duty Cycle PWM Linear Duty Cycle (Note 3) PWM Phase Angle Error VR_RDY (Power Good) Output VR_RDY Saturation Voltage VR_RDY Rise Time
200 kHz < FSW < 600 kHz 100 kHz < FSW <1 MHz 10 mA IROSC 200 mA FS = 800 kHz
% V
- - -
30 20 1.0 1.3 2.3 90 -
40 - - - - - 15
ns ns V V V %
COMP voltage when the PWM outputs remain LOW COMP voltage when the PWM outputs remain HIGH
- - - -15
IVR_RDY = 10 mA External pullup of 680 kW to 1.25 V, CL = 45 pF, DVO = 10% to 90% VR_RDY = 5.0 V VCore increasing, DAC = 1.3 V VCore decreasing, DAC = 1.3 V VCore increasing VCore decreasing
- -
- -
0.4 150
V ns
VR_RDY High - Output Leakage Current VR_RDY Upper Threshold Voltage VR_RDY Lower Threshold Voltage VR_RDY Rising Delay VR_RDY Falling Delay PWM Outputs Output High Voltage
- - - - -
- 300 350 - -
1.0 - - 3 250
mA mV below DAC mV below DAC ms ns
Sourcing 500 mA
3.0
-
VCC
V
3. Guaranteed by design. Not tested in production.
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NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter PWM Outputs Output Low Voltage Rise Time Fall Time Tri-State Output Leakage Output Impedance - Sourcing Output Impedance - Sinking DRVON Output High Voltage Output Low Voltage Rise Time Fall Time Internal Pulldown Resistance Soft-Start Soft-Start Pin Source Current Soft-Start Ramp Time Soft-Start Pin Discharge Voltage VR11 Dwell Time at VBOOT DACMODE Input Input Range for AMD Operating Mode Input Range for VR11 Operating Mode Input Range for VR10 Operating Mode Enable Input Enable High Input Leakage Current Rising Threshold Falling Threshold Hysteresis Enable Delay Time Disable Delay Time Current Limit Current Sense Amp to ILIM Gain ILIM Pin Input Bias Current ILIM Pin Working Voltage Range ILIM Offset Voltage Delay (Note 3) 3. Guaranteed by design. Not tested in production. Offset extrapolated to CSx - CSxN = 0, referred to ILIM pin 20 mV < (CSx - CSxN) < 60 mV (Each CS Input Independently) VILIM = 2.0 V 5.7 - 0.2 -33 - 5.95 - - 17 300 6.2 1.0 2.0 67 - V/V mA V mV ns EN = 3.3 V VUPPER VLOWER VUPPER - VLOWER Time from Enable transitioning HI to initiation of Soft-Start EN Low to DRVON Low - 0.800 0.670 - 1.0 - - - - 130 - 150 1.0 0.920 0.830 - 5.0 200 mA V V mV ms ns 2.3 0.9 0 - - - 3.5 1.7 0.5 V V V CSS = 0.01 mF; Time to 1.05 V DRVON pin = LO (Fault) CSS = 0.01 mF 3.75 - - 50 5.0 2.2 - - 6.25 - 25 500 mA ms mV ms Sourcing 500 mA Sinking 500 mA CL (PCB) = 20 pF, DVO = 10% to 90% CL = 20 pF, DVO = 10% to 90% 3.0 - - - - - - 24 11 70 VCC 0.7 30 20 - V mV ns ns kW Sinking 500 mA CL = 20 pF, DVO = 0.3 to 2.0 V CL = 20 pF, DVO = Vmax to 0.7 V Gx = 2.5 V, x = 1 - 4 Maximum Resistance to VCC Maximum Resistance to GND - - - - - - - - - - 320 140 0.15 20 20 1.5 - - V ns ns mA W W Test Conditions Min Typ Max Units
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NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter Overvoltage Protection Overvoltage Threshold Delay (Note 3) Undervoltage Protection VCC UVLO Start Threshold VCC UVLO Stop Threshold VCC UVLO Hysteresis VID Inputs Upper Threshold Lower Threshold Input Bias Current Delay before Latching VID Change (VID De-Skewing) (Note 3) Internal DAC Slew Rate Limiter Positive Slew Rate Limit Negative Slew Rate Limit Input Supply Current VCC Operating Current Temperature Sensing VR_FAN Upper Voltage Threshold VR_FAN Lower Voltage Threshold VR_FAN Output Saturation Voltage VR_FAN Output Leakage Current NTC Pin Bias Current 12VMON 12VMON (Rising Threshold) 12VMON (Falling Threshold) Sufficient power stage supply voltage Insufficient power stage supply voltage 0.728 0.643 - - 0.821 0.725 V V Fraction of VREF voltage above which VR_FAN output pulls low Fraction of VREF voltage below which VR_FAN output is open ISINK = 4 mA High Impedance State - - - - - 0.4 x VREF 0.33 x VREF - - - - - 0.3 1 1 - - V mA mA EN = LOW, No PWM - - 20 mA VID Step of +500 mV VID Step of -500 mV - - 6.3 -6.3 - - mV/ms mV/ms Measured from the edge of the first VID change VUPPER VLOWER - 300 - 500 - - - - 800 - 500 800 mV mV nA ns 4 3.8 100 - - 215 4.5 4.3 - V V mV DAC+ 160 - - 100 DAC+ 200 - mV ns Test Conditions Min Typ Max Units
3. Guaranteed by design. Not tested in production.
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NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter VRM11 DAC System Voltage Accuracy 1.0 V < DAC < 1.6 V 0.8 V < DAC < 1.0 V 0.5 V < DAC < 0.8 V With CS Input DVIN = 0 V With CS Input DVIN = 0 V With CS Input DVIN = 0 V - - 0.5 5 8 - - - % mV mV mV mV mV Test Conditions Min Typ Max Units
No Load Offset Voltage from Nominal DAC Specification (NCP5386) No Load Offset Voltage from Nominal DAC Specification (NCP5386A) No Load Offset Voltage from Nominal DAC Specification (NCP5386B)
- - -
-19 +20 50
Table 1: VRM11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 VID3 50 mV 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 VID2 25 mV 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Voltage (V) OFF OFF 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375 HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23
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NCP5386, NCP5386A, NCP5386B
Table 1: VRM11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID5 200 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID4 100 mV 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 VID3 50 mV 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 VID2 25 mV 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Voltage (V) 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000 1.09375 1.08750 1.08125 HEX 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55
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NCP5386, NCP5386A, NCP5386B
Table 1: VRM11 VID Codes
VID7 800 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID6 400 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID4 100 mV 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID3 50 mV 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 VID2 25 mV 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 12.5 mV 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Voltage (V) 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125 0.82500 0.81875 0.81250 0.80625 0.80000 0.79375 0.78750 0.78125 0.77500 0.76875 HEX 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87
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NCP5386, NCP5386A, NCP5386B
Table 1: VRM11 VID Codes
VID7 800 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID6 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 VID5 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID4 100 mV 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 VID3 50 mV 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 1 1 VID2 25 mV 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 1 1 VID1 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 VID0 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 Voltage (V) 0.76250 0.75625 0.75000 0.74375 0.73750 0.73125 0.72500 0.71875 0.71250 0.70625 0.70000 0.69375 0.68750 0.68125 0.67500 0.66875 0.66250 0.65625 0.65000 0.64375 0.63750 0.63125 0.62500 0.61875 0.61250 0.60625 0.60000 0.59375 0.58750 0.58125 0.57500 0.56875 0.56250 0.55625 0.55000 0.54375 0.53750 0.53125 0.52500 0.51875 0.51250 0.50625 0.50000 OFF OFF OFF HEX 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 FE FF B3 to FD
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NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter VRM10 DAC System Voltage Accuracy No Load Offset Voltage from Nominal DAC Specification No Load Offset Voltage from Nominal DAC Specification (NCP5386A) No Load Offset Voltage from Nominal DAC Specification (NCP5386B) 1.0 V < DAC < 1.6 V 0.83125 V < DAC < 1.0 V With CS Input DVIN = 0 V With CS Input DVIN = 0 V With CS Input DVIN = 0 V - - - - - -19 +20 50 0.5 5 - - - % mV mV mV mV Test Conditions Min Typ Max Units
Table 2: VRM10 VID Codes
VID4 400 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 VID3 200 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 VID2 100 mV 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 VID1 50 mV 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 VID0 25 mV 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 VID5 12.5 mV 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID6 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal DAC Voltage (V) 1.60000 1.59375 1.58750 1.58125 1.57500 1.56875 1.56250 1.55625 1.55000 1.54375 1.53750 1.53125 1.52500 1.51875 1.51250 1.50625 1.50000 1.49375 1.48750 1.48125 1.47500 1.46875 1.46250 1.45625 1.45000 1.44375 1.43750 1.43125 1.42500 1.41875 1.41250 1.40625 1.40000 1.39375
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NCP5386, NCP5386A, NCP5386B
Table 2: VRM10 VID Codes
VID4 400 mV 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 200 mV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID2 100 mV 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 VID1 50 mV 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 VID0 25 mV 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 VID5 12.5 mV 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 VID6 6.25 mV 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal DAC Voltage (V) 1.38750 1.38125 1.37500 1.36875 1.36250 1.35625 1.35000 1.34375 1.33750 1.33125 1.32500 1.31875 1.31250 1.30625 1.30000 1.29375 1.28750 1.28125 1.27500 1.26875 1.26250 1.25625 1.25000 1.24375 1.23750 1.23125 1.22500 1.21875 1.21250 1.20625 1.20000 1.19375 1.18750 1.18125 1.17500 1.16875 1.16250 1.15625 1.15000 1.14375 1.13750 1.13125 1.12500 1.11875 1.11250 1.10625 1.10000
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NCP5386, NCP5386A, NCP5386B
Table 2: VRM10 VID Codes
VID4 400 mV 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 VID3 200 mV 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 VID2 100 mV 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 VID1 50 mV 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 VID0 25 mV 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 VID5 12.5 mV 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 VID6 6.25 mV 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Nominal DAC Voltage (V) 1.09375 OFF OFF OFF OFF 1.08750 1.08125 1.07500 1.06875 1.06250 1.05625 1.05000 1.04375 1.03750 1.03125 1.02500 1.01875 1.01250 1.00625 1.00000 0.99375 0.98750 0.98125 0.97500 0.96875 0.96250 0.95625 0.95000 0.94375 0.93750 0.93125 0.92500 0.91875 0.91250 0.90625 0.90000 0.89375 0.88750 0.88125 0.87500 0.86875 0.86250 0.85625 0.85000 0.84375 0.83750 0.83125
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NCP5386, NCP5386A, NCP5386B
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated: 0C < TA < 85C; 4.75 V < VCC < 5.25 V; All DAC Codes; CVCC = 0.1 mF) Parameter AMD DAC System Voltage Accuracy No Load Offset Voltage from Nominal DAC Specification 0.8 V < DAC < 1.55 V With CS Input DVIN = 0 V - - - 20 0.5 - % mV Test Conditions Min Typ Max Units
Table 3: AMD VID Codes
VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Nominal VOUT (V) 1.550 1.525 1.500 1.475 1.450 1.425 1.400 1.375 1.350 1.325 1.300 1.275 1.250 1.225 1.200 1.175 1.150 1.125 1.100 1.075 1.050 1.025 1.000 0.975 0.950 0.925 0.900 0.875 0.850 0.825 0.800 Shutdown Tolerance 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 0.5 % 5.0 mV 5.0 mV 5.0 mV 5.0 mV 5.0 mV 5.0 mV 5.0 mV 5.0 mV -
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NCP5386, NCP5386A, NCP5386B
TYPICAL CHARACTERISTICS
1.60 VR_RDY DELAY TIME (ms) 1.58 1.56 1.54 1.52 1.50 0 10 20 30 40 50 60 70 80 90 TA, AMBIENT TEMPERATURE (C) ROSC VOLTAGE (V) 2.017 2.016 2.015 2.014 2.013 2.012
0
10
20
30
40
50
60
70
80
90
TA, AMBIENT TEMPERATURE (C)
Figure 5. PWM Output Resistance vs. Ambient Temperature
4.90 SOFT-START CURRENT (mA) 11.0
Figure 6. ROSC Voltage vs. Ambient Temperature
4.85
SUPPLY CURRENT (mA) 0 10 20 30 40 50 60 70 80 90
10.5
4.80
10.0
4.75
9.5
4.70 TA, AMBIENT TEMPERATURE (C)
9.0 0 10 20 30 40 50 60 70 80 90 TA, AMBIENT TEMPERATURE (C)
Figure 7. Soft-start Current vs. Ambient Temperature
1.003 VCC, UVLO THRESHOLD (V) 4.30
Figure 8. Supply Current vs. Ambient Temperature
Start 4.25 4.20 4.15 4.10 4.05
RSA GAIN (V/V)
1.002
DAC = 1.6 V DAC = 1.1 V
1.001 DAC = 0.5 V 1.000
Stop 0 10 20 30 40 50 60 70 80 90
0
10
20
30
40
50
60
70
80
90
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 9. RSA Gain vs. Ambient Temperature
Figure 10. UVLO Threshold vs. Ambient Temperature
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NCP5386, NCP5386A, NCP5386B
TYPICAL CHARACTERISTICS
0.80 Start 12VMON THRESHOLD (V) ENABLE THRESHOLD (V) 0.78 0.76 0.74 0.72 0.70 0.68 Stop 0 10 20 30 40 50 60 70 80 90 0.90 0.88 0.86 0.84 0.82 0.80 0.78 0.76 0.74 0.72 0 10 20 30 40 50 60 70 80 90 Stop Start
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 11. 12VMON Threshold vs. Ambient Temperature
2.0 85C BIAS ERROR (mV) 1.0 70C 50C 0 25C VDRP SOURCE CURRENT (mA) 1.50 1.45 1.40 1.35 1.30 1.25 2 22 42 62 82 102 122 142 162 0
Figure 12. Enable Threshold vs. Ambient Temperature
-1.0 0C -2.0 DAC CODE
10
20
30
40
50
60
70
80
90
TA, AMBIENT TEMPERATURE (C)
Figure 13. RSA Bias
Figure 14. VDRP Source Current vs. Ambient Temperature
5.795 5.790 VDRP GAIN (V/V) 5.785 5.780 5.775 5.770 5.765 CS1 0 10 20 30 40 50 60 70 80 90 TA, AMBIENT TEMPERATURE (C) CS2
6.35 DAC SLEW RATE (mV/ms) 6.30 FALLING 6.25 6.20 6.15 6.10 6.05 6.00 0 10 20 30 40 50 60 70 80 90 RISING
TA, AMBIENT TEMPERATURE (C)
Figure 15. DAC Slew Rate vs. Ambient Temperature
Figure 16. VDRP Gain vs. Ambient Temperature
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NCP5386, NCP5386A, NCP5386B
TYPICAL CHARACTERISTICS
3.0 360 Lower 350 VDRP OFFSET (mV) THRESHOLD (mV) 2.0 340 330 320 310 -1.0 300 Upper 0 10 20 30 40 50 60 70 80 90
1.0
0
0
10
20
30
40
50
60
70
80
90
TA, AMBIENT TEMPERATURE (C)
TA, AMBIENT TEMPERATURE (C)
Figure 17. VDRP Offset vs. Ambient Temperature
3.0
Figure 18. VR_RDY Thresholds vs. Ambient Temperature
2.0 DEVIATION (%)
SINKING
1.0 SOURCING 0
-1.0 0 10 20 30 40 50 60 70 80 90 TA, AMBIENT TEMPERATURE (C)
Figure 19. PWM Output Resistance vs. Ambient Temperature
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NCP5386, NCP5386A, NCP5386B
FUNCTIONAL DESCRIPTION
General
The NCP5386/A/B dual edge modulated multiphase PWM controller is specifically designed with the necessary features for a high current VR10, VR11 or AMD CPU and chipset power system. The IC consists of the following blocks: Precision Programmable DAC, Differential Remote Voltage Sense Amplifier, High Performance Voltage Error Amplifier, Differential Current Feedback Amplifiers, Precision Oscillator and Triangle Wave Generators, and PWM Comparators. Protection features include Undervoltage Lockout, Soft-Start, Overcurrent Protection, Overvoltage Protection, and Power Good Monitor.
Remote Output Sensing Amplifier (RSA)
Schematic. In 1-Phase mode, gate output G2 must be left open as shown in the 1-phase Applications Schematic. The CS2 and CS2N inputs should be connected to CS1N. The following truth table summarizes the modes of operation:
Gate Output Connections Mode 1-Phase 2-Phase G1 Normal Normal G2 OPEN Normal
These are the only allowable connection schemes to program the modes of operation.
Differential Current Sense Amplifiers
A true differential amplifier allows the NCP5386/A/B to measure VCore voltage feedback with respect to the Vcore ground reference point by connecting the Vcore reference point to VS+, and the Vcore ground reference point to VS-. This configuration keeps ground potential differences between the local controller ground and the Vcore ground reference point from affecting regulation of Vcore between VCore and VCore ground reference points. The RSA also subtracts the DAC (minus VID offset) voltage, thereby producing an unamplified output error voltage at the DIFFOUT pin. This output also has a 1.3 V bias voltage to allow both positive and negative error voltages.
Precision Programmable DAC
A precision programmable DAC is provided. This DAC has 0.5% accuracy over the entire operating temperature range of the part. The DAC can be programmed to support either Intel VR10 or VR11 or AMD K8 specifications. A program selection pin is provided to accomplish this. This pin also sets the startup mode of operation. Connect this pin to 1.25 V to select the VR11 DAC table and startup mode. Connect this pin to ground to select the VR10 DAC table and the VR11 startup mode. Connect this pin to VREF to select the AMD DAC table and startup mode.
High Performance Voltage Error Amplifier
Two differential amplifiers are provided to sense the output current of each phase. The inputs of each current sense amplifier must be connected across the current sensing element of the phase controlled by the corresponding gate output (G1 or G2). If a phase is unused, the differential inputs to that phase's current sense amplifier must be shorted together and connected to CS1N as shown in the 1-Phase Application Schematics. A voltage is generated across the current sense element (such as an inductor or sense resistor) by the current flowing in that phase. The output of the current sense amplifiers are used to control three functions. First, the output controls the adaptive voltage positioning, where the output voltage is actively controlled according to the output current. In this function, all of the current sense outputs are summed so that the total output current is used for output voltage positioning. Second, the output signal is fed to the current limit circuit. This again is the summed current of all phases in operation. Finally, the individual phase current is connected to the PWM comparator. In this way current balance is accomplished.
Oscillator and Triangle Wave Generator
The error amplifier is designed to provide high slew rate and bandwidth. Although not required when operating as the controller of a voltage regulator, a capacitor from COMP to VFB is required for stable unity gain test configurations.
Gate Driver Outputs and 1/2 Phase Operation
The part can be configured to run in 1- or 2-Phase mode. In 2-phase mode, phases 1 and 2 should be used to drive the external gate drivers as shown in the 2-phase Applications
A programmable precision oscillator is provided. The oscillator 's frequency is programmed by the resistance connected from the ROSC pin to ground. The user will usually form this resistance from two resistors in order to create a voltage divider that uses the ROSC output voltage as the reference for creating the current limit setpoint voltage. The oscillator frequency range is 100 kHz/phase to 1.0 MHz/phase. The oscillator generates up to 4 triangle waveforms (symmetrical rising and falling slopes) between 1.3 V and 2.3 V. The triangle waves have a phase delay between them such that for 2-phase operation the PWM outputs are separated by 180 angular degrees, respectively.
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NCP5386, NCP5386A, NCP5386B
PWM Comparators with Hysteresis
Four PWM comparators receive the error amplifier output signal at their noninverting input. Each comparator receives one of the triangle waves offset by 1.3 V at it's inverting input. The output of the comparator generates the PWM outputs G1 and G2. During steady state operation, the duty cycle will center on the valley of the triangle waveform, with steady state duty cycle calculated by VOUT/VIN. During a transient event, both high and low comparator output transitions shift phase to the points where the error amplifier output intersects the down and up ramp of the triangle wave. PROTECTION FEATURES
Undervoltage Lockout
amplifiers. The overcurrent latch is set when the current information exceeds the voltage at the ILIM pin. The outputs are immediately disabled, the VR_RDY and DRVON pins are pulled low, and the soft-start is pulled low. The outputs will remain disabled until the VCC voltage is removed and re-applied, or the ENABLE input is brought low and then high.
Overvoltage Protection and Power Good Monitor
An undervoltage lockout (UVLO) senses the VCC input. During powerup, the input voltage to the controller is monitored, and the PWM outputs and the soft-start circuit are disabled until the input voltage exceeds the threshold voltage of the UVLO comparator. The UVLO comparator incorporates hysteresis to avoid chattering, since VCC is likely to decrease as soon as the converter initiates soft-start.
Overcurrent Shutdown
An output voltage monitor is incorporated. During normal operation, if the voltage at the DIFFOUT pin exceeds 1.3 V, the VR_RDY pin goes low, the DRVON signal remains high, the PWM outputs are set low. The outputs will remain disabled until the VCC voltage is removed and reapplied. During normal operation, if the output voltage falls more than 300 mV below the DAC setting, the VR_RDY pin will be set low until the output rises.
Soft-Start
A programmable overcurrent function is incorporated within the IC. A comparator and latch makeup this function. The inverting input of the comparator is connected to the ILIM pin. The voltage at this pin sets the maximum output current the converter can produce. The ROSC pin provides a convenient and accurate reference voltage from which a resistor divider can create the overcurrent setpoint voltage. Although not actually disabled, tying the ILIM pin directly to the ROSC pin sets the limit above useful levels - effectively disabling overcurrent shutdown. The comparator noninverting input is the summed current information from the current sense
- REMOTE SENSE + AMP VS- VS+ DIFFOUT
The NCP5386 incorporates an externally programmable soft-start. The soft-start circuit works by controlling the ramp-up of the DAC voltage during powerup. The initial soft-start pin voltage is 0 V. The soft-start circuitry clamps the DAC input of the Remote Sense Amplifier to the SS pin voltage until the SS pin voltage exceeds the DAC setting minus VID offset thereafter. The soft-start pin is pulled to 0 V. There are two possible soft-start modes: AMD and VR11. AMD mode simply ramps Vcore from 0 V directly to the DAC setting at the rate set by the capacitor connected to the SS pin. The VR11 mode ramps Vcore to 1.1 V at the SS capacitor charge rate, pauses at 1.1 V for 170 ms, reads the VID pins to determine the DAC setting, then ramps Vcore to the final DAC setting at the Dynamic VID slew rate of 7.3 mV/ms. Typical AMD and VR11 soft-start sequences are shown in the following graphs.
+ ERROR AMP C1 1 nF COMP
1.3 V
- R1 10 k VFB
Figure 20. DAC Servo Evaluation Circuit
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NCP5386, NCP5386A, NCP5386B
2.4 2.2 2.0 1.8 VOLTAGE 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 TIME Vcore Voltage SS Pin Voltage VID Setting
Figure 21. Typical AMD Soft-Start Sequence to Vcore = 1.3 V
2.4 2.2 2.0 1.8 VOLTAGE 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 0 TIME Boot Dwell Time NCP5386 Internal Dynamic VID Rate Limit Vcore Voltage SS Pin Voltage Boot Voltage VID Setting
Figure 22. Typical VR10 & VR11 Soft-Start Sequence to Vcore = 1.3 V
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NCP5386, NCP5386A, NCP5386B
APPLICATION INFORMATION The NCP5386 is a high performance multiphase controller optimized to meet the Intel VR11 Specifications. The demo board for the NCP5386 is available by request. It is configured as a four phase solution with decoupling designed to provide a 1.0 mW load line under a 100 A step load. A schematic is available upon request from ON Semiconductor. Startup Procedure The demo board comes with a Socket 775 and requires an Intel dynamic load tool (VTT Tool) available through a third party supplier, Cascade Systems. The web page is http://www.cascadesystems.net/. Start by installing the test tool software. It's best to power the test tool from a separate ATX power supply. The test tool should be set to a valid VID code of 0.5 V or above in-order for the controller to start. Consult the VTT help manual for more detailed instructions.
Startup Sequence
16. Start the second ATX supply by turning it on and setting the PSON DIP switch low. The green VID lights should light up to match the VTT tool VID setting. 17. Set the VR_ENABLE DIP switch up to start the NCP5386. 18. Check that the output voltage is about 19 mV below the VID setting. Step Load Testing The VTT tool is used to generate the high di/dt step load. Select the dynamic loading option in the VTT test tool software. Set the desired step load size, frequency, duty, and slew rate. See Figures 23 and 24.
1. Make sure the VTT software is installed. 2. Powerup the PC or Laptop do not start the VTT software. 3. Insert the VTT Test Tool adapter into the socket and lock it down. 4. Insert the socket saver pin field into the bottom of the VTT test tool. 5. Carefully line up the tool with the socket in the board and press tool into the board. 6. Connect the scope probe, or DMM to the voltage sense lines on the test tool. When using a scope probe it is best to isolate the scope from the AC ground. Make the ground connection on the scope probe as short as possible. 7. Connect the first ATX supply to the VTT tool. 8. Powerup the first ATX supply to the VTT tool. 9. Start the VTT tool software in VR11 mode with the current limit set to 150 A. 10. Using the VTT tool software, select a VID code that is 0.5 V or above. 11. Connect the second ATX supply to the demo board. 12. Set the VID DIP switches. All the VID switches should be up or open. 13. Set the VR_ENABLE DIP switch down or closed. 14. Set the VR10 DIP switch up or open. 15. Set the VID_SEL switch up or open.
Figure 23. Typical Step Load Response
Figure 24. Typical Load Release Event
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NCP5386, NCP5386A, NCP5386B
Dynamic VID Testing The VTT tool provides for VID stepping based on the Intel Requirements. Select the Dynamic VID option. Before enabling the test set the lowest VID to 0.5 V or greater and set the highest VID to a value that is greater than the lowest VID selection, then enable the test. See Figures 25 through 27. Design Methodology
Decoupling the VCC Pin on the IC
An RC input filter is required as shown in the VCC pin to minimize supply noise on the IC. The resistor should be sized such that it does not generate a large voltage drop between the 12 V supply and the IC. See the schematic values.
Understanding Soft-Start
The controller supports two different startup routines. An AMD ramp to the initial VID code, or a VR11 Ramp to the 1.1 V VID code, with a pause to capture the VID code then resume ramping to target value based on an internal slew rate limit. See Figures 28 and 29. The controller is designed to regulate to the voltage on the SS pin until it reaches the internal DAC voltage. The soft-start cap sets the initial ramp rate using a typical 5.0 mA current. The typical value to use for the soft-start cap (SS), is typically set to 0.01 mF. This results in a ramp time to 1.1 V of 2.2 ms based on Equation 1.
Figure 25. 1.6 to 0.5 Dynamic VID Response dt Css ^ iss ss dvss 1.1 * V dv + ss and iss + 5 * mA dtss 2.2 * ms Css + 0.01 * mF
(eq. 1)
Figure 26. Dynamic VID Settling Time Rising
Figure 28. VR11 Startup
Figure 27. Dynamic VID Settling Time Falling Figure 29. AMD Startup
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NCP5386, NCP5386A, NCP5386B
Programming the Current Limit and the Oscillator Frequency The demo board is set for an operating frequency of approximately 330 kHz. The OSC pin provides a 2.0 V reference voltage which is divided down with a resistor divider and fed into the current limit pin ILIM. Calculate the total series resistance to set the frequency and then calculate the individual values for current limit divider. The series resistors RLIM1 and RLIM2 sink current to ground. This current is internally mirrored into a capacitor
100 90 80 70 ROSC (kW) 60 50 40 30 20 10 0 FOSC (2F, Calculated) 0 200 400 600 FOSC (kHz) 800 1000 1200 FOSC (2F, Measured)
to create an oscillator. The period is proportional to the resistance and frequency is inversely proportional to the resistance. The resistance may be estimated by equation 2.
RTOTAL ^ 24686 30.5 kW ^ 24686 FSW -1.1549 330 -1.1549
(eq. 2)
Figure 30. ROSC vs. FOSC, 2 Phase
The current limit function is based on the total sensed current of all phases multiplied by a gain of 6. DCR sensed inductor current is function of the winding temperature. The best approach is to set the maximum current limit Calculate the current limit voltage:
VILIMIT ^ 6 * I MIN_OCP * DCRTmax )
based on the expected average maximum temperature of the inductor windings.
DCRTmax + DCR25C * (1 ) 0.00393 * C-1 (T max -25 * C)) VIN * VOUT L V OUT L
(eq. 3)
DCRTmax * V out 2 * VIN * F s
*
* (N-1) *
(eq. 4)
Solve for the individual resistors:
RLIM2 + VILIMIT * RTOTAL 2*V
(eq. 5)
RLIM1 + RTOTAL * RLIM2
(eq. 6)
Final Equation for the Current Limit Threshold
2 * V * RLIM2
ILIMIT(Tinductor) ^
RLIM1)RLIM2
5.84 * (DCR25C * (1 ) 0.00393 * C-1(T Inductor-25 * C)))
*
V OUT 2 * V IN * Fs
*
V IN-VOUT L
* (N-1) *
VOUT L
(eq. 7)
The inductors on the demo board have a DCR at 25C of 0.75 mW. Selecting the closest available values of 16.9 kW for RLIM1 and 13.7 kW for RLIM2 yield a nominal operating frequency of 330 kHz and an approximate current limit of 152 A at 100C. The total sensed current can be observed as a scaled voltage at the VDRP pin added to a positive, no-load offset of approximately 1.3 V.
Inductor Selection
When using inductor current sensing it is recommended that the inductor does not saturate by more than 10% at maximum load. The inductor also must not go into hard saturation before current limit trips. The demo board includes a two phase output filter using the T50-8 core from Micrometals with 4turns and a DCR target of 0.75 mW @ 25C. Smaller DCR values can be used, however, current sharing accuracy and droop accuracy decrease as DCR
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NCP5386, NCP5386A, NCP5386B
decreases. Use the excel spreadsheet for regulation accuracy calculations for a specific value of DCR.
Inductor Current Sense Compensation
The NCP5386 uses the inductor current sensing method. This method uses an RC filter to cancel out the inductance
RSENSE(T) +
of the inductor and recover the voltage that is the result of the current flowing through the inductor's DCR. This is done by matching the RC time constant of the current sense filter to the L/DCR time constant. The first cut approach is to use a 0.1 mF capacitor for C and then solve for R.
(eq. 8)
L 0.1 * mF * DCR25C * (1 ) 0.00393 * C-1 * (T-25 * C))
The demo board inductor measured 350 nH and 0.75 mW at room temp. The actual value used for RSENSE was 4.42 kW which matches the equation for RSENSE at approximately 50C. Because the inductor value is a function of load and inductor temperature final selection of R is best done experimentally on the bench by monitoring the VDROOP pin and performing a step load test on the actual solution.
Simple Average PSPICE Model Figure 31.
A simple state average model shown in Figure 32 can be used to determine a stable solution and provide insight into the control system.
E1
+ + --
E 0 GAIN = 6
- + - +
VRamp_min 1.3 V
12 0
1
L
2
DCR (0.85e-3/4)
1
LBRD 100 p
2
RBRD 0.75 m CCer (22e-6*18)
(250e-9/4)
- +
VIN 12 0 4
CBulk (560e-6*10) ESRBulk (7e-3/10) 2 ESLBulk (3.5e-9/10)
Voff
1Aac ESRCer 0Adc (1.5e-3/18) 2 ESLCer (1.5e-9/18) 1
+ -
I1 = 10 I2 = 110 TD = 10u TR = 50n TF = 50n PW = 40u PER = 80u
+ -
I2
CH 22 p RF 4.3 k
RDRP 5.11 k
1
0 CF CFB1 1.5 n 680 p RFB1 100
1E3
Unity Gain BW = 15 MHz R6 1k C3 10.6 n 0
RFB
- +
Voff
1k
+ - +
1.3 Voffset
VOUT
+ -
VDAC 1.25 V 0
-
0
Figure 32.
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NCP5386, NCP5386A, NCP5386B
A complex switching model is available by request which includes a more detailed board parasitic for this demo board.
Compensation and Output Filter Design
The values shown on the demo board are a good place to start for any similar output filter solution. The dynamic performance can then be adjusted by swapping out various individual components. If the required output filter and switching frequency are significantly different, it's best to use the available PSPICE models to design the compensation and output filter from scratch. The design target for this demo board was 1.0 mW out to 2.0 MHz. The phase switching frequency is currently set to 330 kHz. It can easily be seen that the board impedance of 0.75 mW between the load and the bulk capacitance has a large effect on the output filter. In this case the ten 560 mF
bulk capacitors have an ESR of 7.0 mW. Thus the bulk ESR plus the board impedance is 0.7 mW + 0.75 mW or 1.45 mW. The actual output filter impedance does not drop to 1.0 mW until the ceramic breaks in at over 375 kHz. The controller must provide some loop gain slightly less than one out to a frequency in excess 300 kHz. At frequencies below where the bulk capacitance ESR breaks with the bulk capacitance, the DC-DC converter must have sufficiently high gain to control the output impedance completely. Standard Type-3 compensation works well with the NCP5386. RFB1 should be kept above 50 W for amplifier stability reasons. The goal is to compensate the system such that the resulting gain generates constant output impedance from DC up to the frequency where the ceramic takes over holding the impedance below 1.0 mW. See the example of the locations of the poles and zeros that were set to optimize the model above.
Zout Open Loop Zout Closed Loop Open Loop Gain with Current loop Closed
80 60 40 20 0
Voltage Loop Compensation Gain
1/(2*PI*CFB1*(RFB1+RFB)) 1/(2*PI*CF*RF) RF/RFB 1/(2*PI*(RBRD+ESRBulk)*CBulk)
1/(2*PI*RF*CH) Error Amp Open Loop Gain
RF/RFB1
dB
-20 -40 -60 -80 -100 100
1/(2*PI*SQRT(ESL_Cer*CCer)) 1mOhm 1/(2*PI*CCer*(RBRD+ESRBulk))
1000 10000 100000 1000000 10000000
Frequency
Figure 33.
By matching the following equations a good set of starting compensation values can be found for a typical mixed bulk and ceramic capacitor type output filter.
1 1 + 2p * CF * RF 2p * (RBRD ) ESRBulk) * CBulk 1 1 + 2p * CFBI * (RFBI ) RFB) 2p * CCer * (RBRD ) ESRBulk)
(eq. 9)
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NCP5386, NCP5386A, NCP5386B
RFB is always set to 1.0 kW and RFB1 is usually set to 100 W for maximum phase boost. The value of RF is typically set to 4.0 kW.
Droop Injection and Thermal Compensation
RRDP determines the target output impedance by the basic equation:
VOUT RFB * DCR * 6 + Z OUT + IOUT RDRP RFB * DCR * 6 RDRP + ZOUT
(eq. 10)
The VDRP signal is generated by summing the sensed output currents for each phase and applying a gain of approximately six. VDRP is externally summed into the feedback network by the resistor RDRP. This induces an offset which is proportional to the output current thereby forcing the controlled resistive output impedance.
The value of the inductor's DCR varies with temperature according to the following equation 10:
DCRTmax + DCR 25C * (1 ) 0.00393 * C-1(T max * 25 * C))
(eq. 11)
The system can be thermally compensated to cancel this effect out to a great degree by adding an NTC (negative temperature coefficient resistor) in parallel with RFB to reduce the droop gain as the temperature increases. The NTC device is nonlinear. Putting a resistor in series with the
NTC helps make the device appear more linear with temperature. The series resistor is split and inserted on both sides of the NTC to reduce noise injection into the feedback loop. The recommended value for RISO1 and RISO2 is approximately 1.0 kW.
The output impedance varies with inductor temperature by the equation:
ZOUT(T) + RFB * DCR25C * (1 ) 0.00393 * C-1(T max -25C)) * 6 Rdroop
(eq. 12)
By including the NTC RT2 and the series isolation resistors the new equation becomes:
ZOUT(T) +
RFB * (RISO1)RT2(T))RISO2) RFB)RISO1)RT2(T))RISO2
* DCR25C * (1 ) 0.00393 * C-1(T max -25C)) * 6 R droop
(eq. 13)
The typical equation of a NTC is based on a curve fit equation 13.
RT2(T) + RT225C * e b 1 *1 298 273 ) T
(eq. 14)
The demo board is populated with a 10 kW NTC with a Beta of 4300. Figure 34 shows the uncompensated and compensated output impedance versus temperature.
ON Semiconductor provides an excel spreadsheet to help with the selection of the NTC. The actual selection of the NTC will be effected by the location of the output inductor with respect to the NTC and airflow, and should be verified with an actual system thermal solution.
VRFAN
Thermal monitoring provides one threshold sensitive comparator for thermal monitoring. The circuit consists of one comparator that compares the voltage on the NTC pin to an internal resistor divider connected to VCC. The following equations can be used to find the temperature trip points.
RT1(T) + RT125C * e b RatioNTC(T) : 1 *1 298 273 ) T
(eq. 15)
RNTC2 ) RT1(T) RNTC1 ) RNTC2 ) RT1(T)
(eq. 16)
Figure 34. Uncompensated and Compensated Output Impedance vs. Temperature
The demo board contains a 68 K NTC for RT1 with a Beta of 4750. RNTC1 is populated with 15 kW and RNTC2 is populated with a zero ohm resistor. Figure 35 is a plot of Equation 16. The horizontal trip thresholds intersect the
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NCP5386, NCP5386A, NCP5386B
Ratio NTC curve, at the respective activation and deactivation temperature. UVLO threshold. See the state diagram for further details. The OVP circuit monitors the output of DIFFOUT. If the DIFFOUT signal reaches 180 mV above the nominal 1.3 V offset the OVP will trip. The DIFFOUT signal is the difference between the output voltage and the DAC voltage plus the 1.3 V internal offset. This results in the OVP tracking the DAC voltage even during a dynamic change in the VID setting during operation. Gate Driver and MOSFET Selection ON Semiconductor provides the companion gate driver IC (NCP3418B). The NCP3418B driver is optimized to work with a range of MOSFETs commonly used in CPU applications. The NCP3418B provides special functionality and is required for the high performance dynamic VID operation of the part. Contact your local ON Semiconductor applications engineer for MOSFET recommendations. Board Stackup The demo board follows the recommended Intel Stackup and copper thickness as shown.
Figure 35.
OVP The overvoltage protection threshold is not adjustable. OVP protection is enabled as soon as soft-start begins and is disabled when the part is disabled. When OVP is tripped, the controller commands all two gate drivers to enable their low side MOSFETs, and VR_RDY transitions low. In order to recover from an OVP condition, VCC must fall below the
Figure 36.
Board Layout A complete Allegro ATX and BTX demo board layout file and schematics are available by request at www.onsemi.com and can be viewed using the Allegro Free Physical Viewer 15.x from the Cadence website http://www.cadence.com/.
Close attention should be paid to the routing of the sense traces and control lines that propagate away from the controller IC. Routing should follow the demo board example. For further information or layout review contact ON Semiconductor.
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NCP5386, NCP5386A, NCP5386B
PACKAGE DIMENSIONS
QFN32 5*5*1 0.5 P CASE 485AF-01 ISSUE O
A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 3.500 3.650 3.800 5.00 BSC 3.500 3.650 3.800 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
D
2X 2X
0.15 C 0.15 C
0.10 C
32 X
0.08 C
L
32 X 8 9
32 X b 0.10 C A B
0.05 C BOTTOM VIEW
The product described herein (NCP5386), may be covered by one or more of the following U.S. patents: 7,057,381. There may be other patents pending.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative
EE EE
TOP VIEW SIDE VIEW D2
16 1 32 25
PIN ONE LOCATION
E
DIM A A1 A3 b D D2 E E2 e K L
(A3) A A1 C
EXPOSED PAD SEATING PLANE
K
17 32 X
E2
24
e
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NCP5386/D

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